The present embodiments relate to wireless communications systems and, more particularly, to a high frequency programmable frequency divider for frequency modulated (FM) carrier generation for handheld wireless communication systems.
Wireless communications are prevalent in business, personal, and other applications, and as a result the technology for such communications continues to advance in various areas. One such advancement includes the use of spread spectrum communications, including that of code division multiple access (CDMA) which includes wideband code division multiple access (WCDMA) cellular communications. In CDMA communications, user equipment (UE) (e.g., a hand held cellular phone, personal digital assistant, or other) communicates with a base station, where typically the base station corresponds to a “cell.” CDMA communications are by way of transmitting symbols from a transmitter to a receiver, and the symbols are modulated using a spreading code which consists of a series of binary pulses. The code runs at a higher rate than the symbol rate and determines the actual transmission bandwidth. In the current industry, each piece of CDMA signal transmitted according to this code is said to be a “chip,” where each chip corresponds to an element in the CDMA code. Thus, the chip frequency defines the rate of the CDMA code. WCDMA includes alternative methods of data transfer, one being frequency division duplex (FDD) and another being time division duplex (TDD), where the uplink and downlink channels are asymmetric for FDD and symmetric for TDD.
The Global System for Mobile (GSM) communications is another common wireless standard. Most GSM systems use either 900 MHz or 1800 MHz bands. The 900 MHz band is divided into an 890-915 MHz uplink frequency band and a 935-960 MHz downlink frequency band. Each 25 MHz bandwidth is divided into 124 carrier frequency channels spaced 200 kHz apart. Each carrier frequency channel transmits and receives over eight time division multiple access (TDMA) time slots in each TDMA frame. TDMA communications are transmitted as a group of packets in a time period, where the time period is divided into time slots so that multiple receivers may access meaningful information during a different part of that time period. In other words, in a group of TDMA receivers, each receiver is designated a time slot in the time period, and that time slot repeats for each group of successive packets transmitted to the receiver. Accordingly, each receiver is able to identify the information intended for it by synchronizing to the group of packets and then deciphering the time slot corresponding to the given receiver. Given the preceding, CDMA transmissions are receiver-distinguished in response to codes, while TDMA transmissions are receiver-distinguished in response to time slots.
New standards for Digital Video Broadcast (DVB) standards are currently being developed to permit streaming video reception by portable user equipment. DVB typically uses carrier frequencies in the 470-800 MHz band. DVB packets or data streams are transmitted by Orthogonal Frequency Division Multiplex (OFDM) transmission with time slicing. With OFDM, multiple symbols are transmitted on multiple carriers that are spaced apart to provide orthogonality. An OFDM modulator typically takes data symbols into a serial-to-parallel converter, and the output of the serial-to-parallel converter is considered as frequency domain data symbols. The frequency domain tones at either edge of the band may be set to zero and are called guard tones. These guard tones allow the OFDM signal to fit into an appropriate spectral mask. Some of the frequency domain tones are set to values which will be known at the receiver, and these tones are termed pilot tones or symbols. These pilot symbols can be useful for channel estimation at the receiver. An inverse fast Fourier transform (IFFT) converts the frequency domain data symbols into a time domain waveform. The IFFT structure allows the frequency tones to be orthogonal. A cyclic prefix is formed by copying the tail samples from the time domain waveform and appending them to the front of the waveform. The time domain waveform with cyclic prefix is termed an OFDM symbol, and this OFDM symbol may be upconverted to an RF frequency and transmitted. An OFDM receiver may recover the timing and carrier frequency and then process the received samples through a fast Fourier transform (FFT). The cyclic prefix may be discarded and after the FFT, frequency domain information is recovered. The pilot symbols may be recovered to aid in channel estimation so that the data sent on the frequency tones can be recovered.
Present mobile communication systems are also designed to accommodate other services such as amplitude modulated (AM) and frequency modulated (FM) radio reception. FM receivers, in particular, require high frequency, low power frequency synthesizers to reproduce the FM carrier in a local oscillator (LO). An efficient low power frequency divider that may be used in a phase locked loop for high frequency applications was disclosed by Vaucher et al., “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 7, pp. 1039-1045, (July 2000). Referring to FIG. 1, there is an exemplary programmable divider as disclosed by Vaucher et al. The divider includes individual ⅔ cells 100-106. The series connected cells receive clock signal CLK at lead 108 and produce divided clock signal CLK_DIV at lead 110. Each cell responds to a respective mode signal MOD0-MOD3 and a respective program bit B0-B3. The CLK_DIV signal and mode signals MOD0-MOD3 are shown at FIG. 2. Each mode pulse has a width equal to the input clock period of the cell. If a program bit, for example B0 of cell 100, is equal to logic 0, the ⅔ cell 120 divides the input frequency by 2. Alternatively, if the program bit B0 is equal to logic 1, the ⅔ cell 120 divides the input frequency by 3. Timing of cell 100 is determined by the output of AND gate 122, which is a logical AND of mode signal MOD0 and program bit B0.
Referring now to FIG. 3, there is a schematic of a ⅔ cell as disclosed by Vaucher et al. The ⅔ cell includes a prescaler logic block 300 and an end-of-cycle logic block 320. The prescaler logic block 300 includes AND gate 304 and delay flip-flops 306 and 308. The end-of-cycle logic block 320 includes AND gates 332 and 326 and delay flip-flops 330 and 324. All flip-flops are clocked by input frequency Fin at lead 302. In operation, the end-of-cycle logic block 320 performs two functions. First, it passes the mode signal at lead 334 to the previous ⅔ cell on lead 322 in response to the true output (Q) from latch 308 and a low-to-high transition of Fin. Second, it produces an inversion of the signal on lead 322 at lead 303 in response to a high-to-low transition of Fin.
When the signal on lead 303 is high, AND gate 304 passes the output signal Fout at lead 310 to flip-flop 306. Flip-flop 306 latches the input signal on a low-to-high transition of Fin at lead 302. A subsequent high-to-low transition of Fin latches the true output (Q) of flip-flop 306 in flip-flop 308 to invert the signal Fout at the complementary output (/Q) of flip-flop 308. Thus, two transitions of Fin at lead 302 produce a single transition of Fout at lead 310 when the signal at lead 303 is high and the ⅔ cell divides Fin by two. Alternatively, when the signal on lead 303 is low, AND gate 304 does not pass the signal at Fout to latch 306 for another cycle, and the ⅔ cell divides Fin by three.
Although the ⅔ series cells of Vaucher et al. is very efficient, it does have limitations for certain applications. For example, the output frequency has an asymmetrical duty cycle that gets progressively worse with subsequent frequency divisions. This is evident from FIG. 6 of Vaucher et al. Another limitation is that a straightforward implementation of the ⅔ series cells may have insufficient loop bandwidth or excess phase noise for certain frequency synthesis applications.